The present invention pertains generally to the field of computer systems and more particularly to a system and method for length decode to detect one-byte prefixes and branch type macro-instructions.
Processors (including, but not limited to, general and special purpose microprocessors, micro-controllers, and digital signal processors (DSPs)) typically include execution units that execute a sequence of instructions, termed micro-instructions, derived from a computer program. Many computer programs are written in a high level language that is not directly executable by the central processing unit (CPU) of a computer and the instructions of such programs must accordingly be decoded into a form suitable for execution by the CPU. For example, a program may be written in a high level language such as C, C++, or Java, and then compiled into a corresponding sequence of macro-instructions, which are in turn decoded into micro-instructions for eventual execution. Programs can also be written directly of a series of macro-instructions (that is, machine code).
Macro-instructions are commonly stored as contiguous data blocks in a memory resource, such as main memory (ergo, RAM) or in a cache, for retrieval and supplied to a decoder unit within a processor for decoding into micro-instructions. To enable the decoder unit to decode macro-instructions successfully, it will be appreciated that it is necessary to identify instruction boundaries within retrieved data blocks, that constitute the instruction stream, that indicate where one macro-instruction ends and the next begins.
In reduced instruction set computer (RISC) processor architectures and instruction sets, macro-instructions typically have a fixed length, in which case the boundaries between instructions can be determined with relative ease once an initial boundary is identified, as each instruction has a known length. For a variable-length instruction set, once an initial boundary location is identified, the length of each macro-instruction must be ascertained to identify subsequent instruction boundaries. The task of identifying boundaries is further complicated by a variable-length instruction set that, for the purposes of supporting legacy programs, supports multiple data and addressing sizes.
In one type of reduced instruction set processor, instructions may have one or more prefix bytes preceding an instruction which modify the operation of the instruction. In this type of instruction set, one-byte prefixes occur frequently, however, decoding such instructions add an additional cycle to the decoding process. In addition, when branch instructions are present, instruction flow may need to be redirected to the correct path. In this respect, branch instructions often lead to cycle delays.
A system and method for pre-decoding one-byte instruction prefixes and branch instruction indicators is described. A static line detect generates a number of instruction indicators. Further, a prefix and branch decode unit combines at least two of the number of instruction indicators, and a pre-decode unit decodes the combined instruction indicators.